1. Field
Example embodiments relate to methods of manufacturing semiconductor devices.
2. Description of the Related Art
As the integration degree of a semiconductor device increases, the formation of patterns having minute line widths is desirable. In addition, as the line width decreases, it may become more difficult to reduce mis-alignment.
When an opening is formed by etching a layer including crystalline silicon, the sidewall of the opening may be formed along a grain boundary to adversely increase the roughness of the sidewall. When the opening is formed by etching a layer including amorphous silicon, the transmittance of the etch target layer may be low, which can deteriorate an alignment.